Memory devices including three-dimensionally arranged memory cells have been developed. For example, a NAND-type nonvolatile memory device has a structure in which a semiconductor channel passes through a plurality of stacked word lines and a memory cell is formed where the semiconductor channel intersects each word line in the stack. When such a memory cell is utilized as a multivalue memory cell, it is desirable that the threshold values of the memory cells change uniformly with respect to a program voltage which is supplied between the semiconductor channel and the word lines. However, variation in the shape of the semiconductor channel along the stacking direction is inevitable due to manufacturing process limitations and resulting deviations in the threshold voltage of the memory cells in the stack sometimes pose an obstacle to using the memory cell as a multivalue memory cell.